Target devices such as field programmable gate arrays (FPGAs), structured application specific integrated circuits (ASICs), and ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices.
Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are high-level compilation and hardware description language (HDL) compilation. High-level compilation (or “high-level synthesis”) involves generating an HDL of a system from a computer language description of the system. The computer language description of the system may be, for example, in Open Computing Language (OpenCL) format or another computer language description format. OpenCL is a framework for writing programs that execute across heterogeneous platforms. OpenCL includes a language for writing kernels and application programming interfaces (APIs) that are used to define and control platforms. HDL compilation involves performing synthesis, placement, routing, and timing analysis of the system on the target device.
Traditionally, high-level synthesis is performed independent of information from other compilations. As a result, the HDL compiler must compile the generated HDL from the high-level compilation in a vacuum in the best manner it can.